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Responsibilities Use data analytics to identify supply chain performance issues and drive actions Analyze demand trends, backlog, bookings etc. against historical trends to identify anomalies Publish and monitor supply chain Key Performance Indicators (KPIs) Create process documentation Monitor supply chain plans vs. actuals to identify variance and drive actions Ad hoc p
Posted 1 day ago
The successful candidate must be both a strategic/visionary leader as well as a hands on contributor with ability to effectively execute plans. Critical to this role is the ability to collaborate cross functionally, agility and flexibility to pivot as business priorities shift, and effectively balance competing priorities. Understand the company's strategy, identify enter
Posted 1 day ago
Marvell is seeking an RF and Analog Design Engineer to contribute to the development of multi tens of GHz TIAs and Drivers. These optical interface chips are tightly coupled with our high performance equalizers. The results of our innovative designs have made our TIAs and Drivers best in class for coherent long haul and metro systems as well as PAM4 data center systems. C
Posted 1 day ago
The IP program Manager will be part of Central Engineering's program management team responsible for the IP development and delivery for Marvell's products and ASIC businesses, giving the opportunity to contribute to the successes of numerous Marvell programs The successful candidate will understand the SoC IP needs and develop plans to deliver and support the IP from con
Posted 1 day ago
In this position, the candidate is expected to join efforts to deliver Marvell's next generation automotive/copper PHY AFE design. As an important contributor, the candidate will participate in designing next generation power efficient multi gigabit automotive/ethernet PHY AFE and building its crucial analog blocks in compliance with various IEEE Base T/T1 standards. As p
Posted 1 day ago
Job Responsibilities To be able to develop monitor/scoreboard/testcases independently. To be able to debug Testcases To be able to verify functionality as per specification To be able to review waveforms during debug to analyze the flow of transactions Requirements Typically requires a Bachelor's degree in Computer Engineering, Electrical Engineering or related fields, or
Posted 2 days ago
Design and develop the firmware for Marvell OCTEON DPU management sub system based on RTOS or Bare metal. Design and develop software/firmware for the Baseboard Management Controller (BMC) based on OpenBMC or RTOS. Implement the platform management communication protocol for the management sub system and the board management controller. Work with qualification team to tes
Posted 2 days ago
Design and develop the firmware for Marvell OCTEON DPU management sub system based on RTOS or Bare metal. Design and develop software/firmware for the Baseboard Management Controller (BMC) based on OpenBMC or RTOS. Implement the platform management communication protocols for the management sub system and the board management controller. Work with qualification team to te
Posted 2 days ago
Contribute as an ASIC Verification Engineer developing the next generation of cloud, networking, and security processors. Work with Architects and Designers to develop complex verification environments, learning and using thelatest state of the art techniques, to prove the design and architecture and discover problems and suggest improvements. Requirements Strong programm
Posted 2 days ago
Marvell utilizes a range of System Level Test equipment hardware platforms to develop and test the various Automotive, Enterprise and Data Center product lines. The Test Operations group maintains these platforms as well as other equipment to support the testing operations. Duties and Responsibilities Responsible for maintaining System Level Test racks and Handler Bring u
Posted 2 days ago
Develop test plans for verification based on architecture and design specifications. Develop testbench components in Systemverilog, UVM, C, and C++. Write tests in Systemverilog, UVM, C, C++, python to test various logical features in ASIC and SOC design blocks. Debug failures in tests and root cause issues with test environment and design. Analyze functional and structur
Posted 2 days ago
The ideal candidate will have 10+ years of related experience and be a technically curious self starter who is excited to think outside the box to work on new technologies and novel solutions. Specific technical skills or experience required for this position are Solid understanding of scan and mbist DFT test methodologies. Design of complex and high performance ATE hardw
Posted 2 days ago
Comfortable interacting one to one with individual technical contributors, senior leaders, as well as coaching teams. Help engineering teams go from fighting fires to avoiding them. You will not only help teams be more efficient, you will see the big picture and ensure processes scale appropriately with the company. Create a collaborative work environment that fosters aut
Posted 2 days ago
As an ASIC Integration Engineer, you will have responsibilities spanning various aspects of SOC design Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation. Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints
Posted 2 days ago
Marvell Semiconductor, Inc.
- Santa Clara, CA / Marlborough, MA
As the leader of the SoC Solution Modeling team, you will have the opportunity to Drive the functional and performance analysis of next generation automotive and networking platforms Lead the development of systems and software platform for software defined vehicles and connected cars Lead the team to develop, integrate, test, and deliver a virtual platform for designing
Posted 2 days ago
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